- ALJ Gildea Issues Claim Construction Order In Certain Dynamic Random Access Memory And NAND Flash Memory Devices (337-TA-803)
- September 18, 2012 | Authors: Christopher Ricciuti; Eric W. Schweibenz
- Law Firm: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P. - Alexandria Office
On August 21, 2012, ALJ E. James Gildea issued the public version of Order No. 65 (dated August 8, 2012) construing the disputed terms of the asserted claims in Certain Dynamic Random Access Memory and NAND Flash Memory Devices and Products Containing Same (Inv. No. 337-TA-803).
By way of background, this investigation is based on a July 12, 2011 complaint filed on behalf of Intellectual Ventures Management, LLC, Invention Investment Fund I, L.P., Invention Investment Fund II, LLC, Intellectual Ventures I LLC, and Intellectual Ventures II LLC (collectively, “IV”), against several manufacturers, distributors, and retailers of DRAM and NAND Flash memory devices for alleged infringement of U.S. Patent Nos. 5,654,932 (the ‘932 patent); 5,963,481 (the ‘481 patent); 5,982,696 (the ‘696 patent); 5,500,819 (the ‘819 patent); and 5,687,132 (the ‘132 patent). See our September 9, 2011 post for more details on the investigation.
The ‘932 Patent
The ‘932 patent discloses “memory devices, systems, and methods by which different modes may be used for accessing memory locations.” The parties disputed the construction of the terms “type of access” and “separately addressable groups.” As to the first term, “type of access,” the ALJ construed the term to mean “mode of access,” as proposed by IV. The ALJ rejected Respondents’ attempt to limit the term to three illustrative types of accesses defined in the specification. ALJ Gildea determined that a person of ordinary skill in the art would recognize the term as encompassing a variety of other access types. As to the term “separately addressable groups,” the ALJ construed the term to mean “groups that can be selected by separate addresses,” as also proposed by IV.
The ‘481 Patent
The ‘481 patent discloses “integrated circuit memory devices in which an Enhanced Dynamic Random Access Memory device and program unit, or other logic element, are embedded together on a common substrate.” The parties disputed the construction of the terms “accessing the data stored at the memory locations,” and “generating a first/second access request [for accessing data]” / “generating the first access request.”
As to the first term, the ALJ determined that “accessing the data stored at the memory locations” required no construction because the term would have been readily understandable to persons of ordinary skill in the art at the time of invention. In particular, ALJ Gildea found that the term “accessing” has a generally understood meaning and should not be limited to “obtaining,” as proposed by Respondents. As to the terms “generating a first/second access request [for accessing data]” and “generating the first access request,” the ALJ also determined that the terms should be given their plain and ordinary meaning.
The ‘696 Patent
The ‘696 patent discloses “a memory comprising an array of memory cells, an address decoder for accessing a selected one of the cells in response to at least one address bit and a programmable array for selectively presenting the at least one address bit to the address decoder in response to a control signal.” The parties disputed the construction of the following terms: (1) “programmable volatile storage array” / “programmable volatile memory cell array” / “programmable memory cell array” / “programmable array;” (2) “selectively redirecting;” (3) “hardwired address decoder;” (4) “control signal” / “decode control signal;” and (5) “accessing a selected one of said cells” / “selecting row of said array for access” / “selecting a column of said array for access” / “accessing said cells in said array.”
With respect to the “programmable array” terms, the ALJ determined that no construction was required, rejecting Respondents’ argument that the appropriate construction should define the specific claim features that are “programmable.” As to the term “selectively redirecting,” the ALJ gave the term its plain and ordinary meaning. As to the term “hardwired address decoder,” the ALJ construed the term to mean “hardwired circuitry that selects a memory cell for access in response to address information,” as proposed by IV. Specifically, ALJ Gildea rejected Respondents’ argument that the patentee limited its invention to a hardwired address decoder that “selects a row or column in the array of memory cells in response to an input row or column” simply because the patentee, in the background of the invention section, noted the absence of this feature in the prior art.
With respect to the “control signal” terms, the ALJ construed the terms to mean “a signal that influences,” as proposed by IV and in accordance with the common meaning of the term as understood by a person of ordinary skill in the art. With respect to the “accessing/selecting” terms, the ALJ determined that no construction was necessary as the terms would have been understood “verbatim” by a person of ordinary skill in the art.
The ‘819 Patent
The ‘819 patent discloses “circuits, systems, and methods for improving accesses and block transfers in a memory system.” The parties disputed the meaning of the terms “sense amplifier” and “sensing the bitlines of the array.” As to the term “sense amplifier,” the ALJ construed the term in accordance with its plain and ordinary meaning, determining that Respondents’ proposed constructions improperly incorporated limitations from the preferred embodiments into the claims and made certain dependent claim language superfluous. In the same manner, the ALJ determined that the term “sensing the bitlines of the array” should be given its plain and ordinary meaning.
The ‘132 Patent
The ‘132 patent relates to multiple-bank memories and systems. The parties disputed the meaning of the terms “coupling said bitlines” / “coupling selected groups of said bitlines” / “coupling selected ones of the bitlines” / “to couple the sensed data from one of the bitlines of the first subarray to the selected one of the bitlines of the second subarray,” and “transfer” or “transferring.” As before, the ALJ refused to adopt any of the limiting language proposed by Respondents and determined that both sets of claim terms should be given their plain and ordinary meaning. In particular, the ALJ rejected Respondents’ argument that the term “coupling ... bitlines” should be limited to “sharing charges between bitlines” as the term “sharing charges” appears nowhere in the ‘132 patent and there was not an unequivocal disavowal of claim scope to support Respondents’ prosecution disclaimer argument.