Vimal M. Kapadia

Vimal M. Kapadia: Attorney with Greenberg Traurig, LLP
  • Law Clerk/JD at Greenberg Traurig, LLP (2025 Attorneys)
  • MetLife Building, 200 Park Avenue, New York, NY 10166
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Biography

Vimal M. Kapadia is an associate in the Intellectual Property & Technology Practice of the firm s New York office. Vimal focuses his practice on complex patent litigation and prosecution involving a broad range of technologies, including electrical arts pertaining to mechanical systems, computer architecture, medical devices, Internet applications, mobile operating systems, wireless communications and user interfaces. He has represented clients in various litigations in federal court, as well as before the International Trade Commission. He also advises clients on all aspects of patentability and provides patent counseling regarding invalidity, non-infringement and freedom to operate assessments.

Prior to practicing law, Vimal was computer chip designer and software engineer at IBM. Vimal is fluent reading and writing source code and is an inventor on six U.S. patents in the fields of cross-model verification and computer chip design.

Concentrations

•Patent litigation
•General IP counseling, licensing, due diligence, and opinions
•Post-issuance patent proceedings, including inter partes review, post-grant review, covered business method patents and ex parte reexaminations

Areas of Practice (2)

  • Intellectual Property & Technology
  • Intellectual Property Litigation

Education & Credentials

Contact Information:
212.801.2241  Phone
212.801.6400  Fax
www.gtlaw.com/People/Vimal-M-Kapadia
University Attended:
Rutgers College, B.S., Electrical and Computer Engineering, with honors, 2001
Law School Attended:
Fordham University School of Law, J.D., Research Assistant, Intellectual Property Courses, 2011-2012, 2012
Year of First Admission:
2012
Admission:
U.S. Patent and Trademark Office; New York; New Jersey
Reported Cases:
Experience: Previous Experience: Advisory Engineer, International Business Machines (IBM), zSeries/S390, 2001-2013; Software Engineer, Microsoft Corp., Terminal Server, Summer 2000; Issued Patents: Patent, Method, computer program product, and hardware product for eliminating or reducing operand line crossing penalty, U.S. Patent No. 9,201,655, December 1, 2015; Patent, Processor error checking for instruction data, U.S. Patent No. 8,201,067, June 12, 2012; Patent, Processor and method for synchronous load multiple fetching sequence and pipeline stage result tracking to facilitate early address generation interlock bypass, U.S. Patent No. 7,987,343, July 26, 2011; Patent, Recycling long multi-operand instructions, U.S. Patent No. 7,962,726, June 14, 2011; Patent, Method, system and computer program product for failure analysis implementing automated comparison of multiple reference models, U.S. Patent No. 7,908,518, March 15, 2011; Patent, Method and system for implementing store buffer allocation, U.S. Patent No. 7,870,314, January 11, 2011
ISLN:
922587825

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New York, New York

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