• ALJ Essex Issues Claim Construction Order in Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers (337-TA-661)
  • July 10, 2009 | Authors: Eric W. Schweibenz; John F. Presper
  • Law Firm: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P. - Alexandria Office
  • On June 22, 2009, ALJ Theodore R. Essex issued Order No. 12, construing the disputed terms of the asserted claims of the patents-in-suit in Certain Semiconductor Chips Having Synchronous Dynamic Random Access Memory Controllers and Products Containing Same (Inv. No. 337-TA-661).

    In this investigation, Complainant Rambus, Inc. (“Rambus”) alleges that respondents NVIDIA Corp.; Asustek Computer Inc.; ASUS Computer International, Inc.; BFG Technologies, Inc.; Biostar Microtech (U.S.A.) Corp.; Biostar Microtech International Corp.; Diablotek Inc.; EVGA Corp.; G.B.T. Inc.; Giga-byte Technology Co., Ltd.; Hewlett-Packard Co.; MSI Computer Corp.; Micro-star International Co., Ltd.; Palit Multimedia Inc.; Palit Microsystems Ltd.; Pine Technology Holdings, Ltd.; and Sparkle Computer Co., Ltd. (“Respondents”) infringe certain claims of U.S. Patent Nos., 7,177,998; 7,210,016; 6,470,405; 6,591,353; 7,287,109; 7,287,119; 7,330,952; 7,330,953; and 7,360,050.  The patents-in-suit are generally directed to memory controllers for controlling data transfers to and from dynamic random access memory in computer systems.  A Markman hearing was held on March 24, 2009.

    Agreeing with the Commission Investigative Staff (the “Staff”), the ALJ made the following findings with respect to the claim terms “signal” and “strobe signal”:  “a strobe signal . . . to initiate sampling of a first portion of the data by the memory device” means a timing signal to initiate sampling of a first portion of the data by the memory device; “an external strobe signal . . . to signal the memory device to sample data” means a timing signal to signal the memory device to sample data; “a signal . . . wherein the signal indicates when the memory device is to begin sampling write data” means a signal that indicates when to begin sampling write data in the memory device; “a signal . . . wherein the signal indicates when the memory device is to begin receiving write data” means a signal that indicates when to begin receiving write data in the memory device; and “a signal . . . wherein the signal indicates when the memory device is to begin the transfer operation” means a signal that indicates when to begin a transfer operation in the memory device.  The ALJ found that “strobe signal” need not be construed to specifically exclude a “clock signal” as asserted by Rambus, and that it need not be construed to necessarily include a “terminate signal” as asserted by Respondents.

    The ALJ agreed with Rambus and the Staff and found that the term “delaying for an amount of time” should be given its plain and ordinary meaning and should not be limited to only variable delays, as asserted by Respondents.

    In addition, the ALJ agreed with Rambus and found that the term “memory core” means storage area of the memory device that includes memory cells and support circuitry for receiving and performing memory options, such as row decoders, column decoders, and sense amplifiers.

    The ALJ further agreed with Rambus and the Staff and found that the term “a first memory device via a first dedicated signal path” means a first signal path that carries data and connects the memory controller and the first memory device but not the second memory device, and that the term “a second memory device via a second dedicated data signal path” means a second signal path that carries data and connects the memory controller and the second memory device but not the first memory device, thus rejecting Respondents’ assertion that a “dedicated” path may be connected to one and only one memory device.

    Again agreeing with Rambus and the Staff, the ALJ made the following findings with respect to “timing circuitry”:  “timing circuitry to delay reception of data signals” means circuitry that delays reception of data signals on each of the data signal paths; and “timing circuitry to delay the transmission of data signals” means circuitry that delays transmission of data signals on each of the data signal paths.

    Moreover, the ALJ agreed with Rambus and the Staff and found that the term “receiving a [first or second] data signal from the [first or second] memory device . . . after delaying for a [first or second] time interval” means receiving a first data signal from the [first or second] memory device via a first data signal path after delaying the signal for a [first or second] amount of time.

    Finally, the ALJ agreed with Rambus and the Staff and found that the term “a [first or second] data reception circuit to receive [first or second] read data from [first or second] memory device . . . after delaying for a [first or second] period of time” means a circuit that receives first read data from a [first or second] memory device . . . after delaying for a [first or second] amount of time.